7-640 tm CD14538BMS cmos dual precision monostable multivibrator description CD14538BMS dual precision monostable multivibrator provides stable retrigger- able/resettable one-shot operation for any fixed-voltage timing application. an external resistor (r x ) and an external capacitor (c x ) control the timing and accuracy for the circuit. adjustment of r x and c x provides a wide range of out- put pulse widths from the q and q terminals. the time delay from trigger input to output transition (trigger propagation delay) and the time delay from reset input to output transition (reset propagation delay) are independent of r x and c x . pre- cision control of output pulse widths is achieved through linear cmos tech- niques. leading-edge-triggering (+tr) and trailing-edge-triggering (-tr) inputs are pro- vided for triggering from either edge of an input pulse. an unused +tr input should be tied to vss. an unused -tr input should be tied to vdd. a reset (on low level) is provided for immediate termination of the output pulse or to pre- vent output pulses when power is turned on. an unused reset input should be tied to vdd. however, if an entire section of the CD14538BMS is not used, its inputs must be tied to either vdd or vss. see table 1. in normal operation the circuit retriggers (extends the output pulse one period) on the application of each new trigger pulse. for operation in the non-retrigger- able mode, q is connected to -tr when leading-edge triggering (+tr) is used or q is connected to +tr when trailing-edge triggering (-tr) is used. the time period (t) for this multivibrator can be calculated by: t = r x c x . the minimum value of external resistance, r x is 4k ? . the minimum and maxi- mum values of external capacitance, c x , are 0pf and 100 f, respectively. the CD14538BMS is interchangeable with type mc14538 and is similar to and pin-compatible with the cd4098b* and cd4538b**. * t = 0.5 r x c x for c x 1000pf. *t = r x c x ; c x min = 5000pf. the CD14538BMS is supplied in these 16-lead outline packages: braze seal dip h4x frit seal dip h1l ceramic flatpack h6w features ? high-voltage type (20v rating) retriggerable/resettable capability trigger and reset propagation delays inde- pendent of rx, cx triggering from leading or trailing edge q and q buffered outputs available separate resets wide range of output-pulse widths schmitt-trigger input allows unlimited rise and fall times on +tr and -tr inputs 100% tested for maximum quiescent cur- rent at 20v maximum input current of 1 a at 18v over full package-temperature range: - 100na at 18v and +25 o c noise margin (full package-temperature range): - 1v at vdd = 5v - 2v at vdd = 10v - 2.5v at vdd = 15v 5v, 10v and 15v parametric ratings standardized symmetrical output charac- teristics meets all requirements of jedec tentative standards no. 13b, ?standard specifica- tions for description of ?b? series cmos device?s applications pulse delay and timing pulse shaping november 1994 fn3192 pinout CD14538BMS top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c x1 r x c x (1) reset (1) +tr (1) -tr (1) q1 v ss q1 v dd r x c x (2) reset (2) +tr (2) -tr (2) q2 q2 c x2 functional diagram mono 1 mono 2 cx1 rx1 vdd 2 1rxcx(1) 6 7 10 9 4 5 3 12 11 13 15 14 rxcx(2) vdd cx2 rx2 q1 q1 q2 q2 +tr -tr reset +tr -tr reset vdd = 16 vss = 8 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
7-641 specifications CD14538BMS absolute maximum ratings reliability information dc supply voltage range, (vdd) . . . . . . . . . . . . . . . -0.5v to +20v (voltage referenced to vss terminals) input voltage range, all inputs . . . . . . . . . . . . .-0.5v to vdd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c package types d, f, k, h storage temperature range (tstg) . . . . . . . . . . . -65 o c to +150 o c lead temperature (during soldering) . . . . . . . . . . . . . . . . . +265 o c at distance 1/16 1/32 inch (1.59mm 0.79mm) from case for 10s maximum thermal resistance . . . . . . . . . . . . . . . . ja jc ceramic dip and frit package . . . . . 80 o c/w 20 o c/w flatpack package . . . . . . . . . . . . . . . . 70 o c/w 20 o c/w maximum package power dissipation (pd) at +125 o c for ta = -55 o c to +100 o c (package type d, f, k) . . . . . . 500mw for ta = +100 o c to +125 o c (package type d, f, k) . . . . . derate linearity at 12mw/ o c to 200mw device dissipation per output transistor . . . . . . . . . . . . . . . 100mw for ta = full package temperature range (all package types) junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c table 1. dc electrical performance characteristics parameter symbol conditions (note 1) group a subgroups temperature limits units min max supply current idd vdd = 20v, vin = vdd or gnd 1 +25 o c-10 a 2+125 o c - 1000 a vdd = 18v, vin = vdd or gnd 3 -55 o c-10 a input leakage current iil vin = vdd or gnd vdd = 20 1 +25 o c -100 - na 2+125 o c -1000 - na vdd = 18v 3 -55 o c -100 - na input leakage current iih vin = vdd or gnd vdd = 20 1 +25 o c-100na 2+125 o c - 1000 na vdd = 18v 3 -55 o c-100na output voltage vol15 vdd = 15v, no load 1, 2, 3 +25 o c, +125 o c, -55 o c- 50 mv output voltage voh15 vdd = 15v, no load (note 3) 1, 2, 3 +25 o c, +125 o c, -55 o c14.95 - v output current (sink) iol5 vdd = 5v, vout = 0.4v 1 +25 o c0.53-ma output current (sink) iol10 vdd = 10v, vout = 0.5v 1 +25 o c1.4-ma output current (sink) iol15 vdd = 15v, vout = 1.5v 1 +25 o c3.5-ma output current (source) ioh5a vdd = 5v, vout = 4.6v 1 +25 o c--0.53ma output current (source) ioh5b vdd = 5v, vout = 2.5v 1 +25 o c--1.8ma output current (source) ioh10 vdd = 10v, vout = 9.5v 1 +25 o c--1.4ma output current (source) ioh15 vdd = 15v, vout = 13.5v 1 +25 o c--3.5ma n threshold voltage vnth vdd = 10v, iss = -10 a1+25 o c-2.8-0.7v p threshold voltage vpth vss = 0v, idd = 10 a1+25 o c0.72.8v functional f vdd = 2.8v, vin = vdd or gnd 7 +25 o cvoh > vdd/2 vol < vdd/2 v vdd = 20v, vin = vdd or gnd 7 +25 o c vdd = 18v, vin = vdd or gnd 8a +125 o c vdd = 3v, vin = vdd or gnd 8b -55 o c input voltage low (note 2) vil vdd = 5v, voh > 4.5v, vol < 0.5v 1, 2, 3 +25 o c, +125 o c, -55 o c- 1.5 v input voltage high (note 2) vih vdd = 5v, voh > 4.5v, vol < 0.5v 1, 2, 3 +25 o c, +125 o c, -55 o c3.5 - v input voltage low (note 2) vil vdd = 15v, voh > 13.5v, vol < 1.5v 1, 2, 3 +25 o c, +125 o c, -55 o c- 4 v input voltage high (note 2) vih vdd = 15v, voh > 13.5v, vol < 1.5v 1, 2, 3 +25 o c, +125 o c, -55 o c11 - v notes: 1. all voltages referenced to device gnd, 100% testing being implemented. 2. go/no go test with limits applied to inputs 3. for accuracy, voltage is measured differentially to vdd. limit is 0.050v max.
7-642 specifications CD14538BMS table 2. ac electrical performance characteristics parameter symbol conditions (note 1, 2) group a subgroups temperature limits units min max propagation delay +tr or -tr to q or q tphl1 tplh1 vdd = 5v, vin = vdd or gnd 9 +25 o c-600ns 10, 11 +125 o c, -55 o c- 810 ns propagation delay reset to q or q tphl2 tplh2 vdd = 5v, vin = vdd or gnd 9 +25 o c-500ns 10, 11 +125 o c, -55 o c- 675 ns transition time tthl ttlh vdd = 5v, vin = vdd or gnd 9 +25 o c-200ns 10, 11 +125 o c, -55 o c- 270 ns notes: 1. cl = 50pf, rl = 200k, input tr, tf < 20ns. 2. -55 o c and +125 o c limits guaranteed, 100% testing being implemented. table 3. electrical performance characteristics parameter symbol conditions notes temperature limits units min max supply current idd vdd = 5v, vin = vdd or gnd 1, 2 -55 o c, +25 o c- 5 a +125 o c-150 a vdd = 10v, vin = vdd or gnd 1, 2 -55 o c, +25 o c- 10 a +125 o c-300 a vdd = 15v, vin = vdd or gnd 1, 2 -55 o c, +25 o c- 10 a +125 o c-600 a output voltage vol vdd = 5v, no load 1, 2 +25 o c, +125 o c, -55 o c -50mv output voltage vol vdd = 10v, no load 1, 2 +25 o c, +125 o c, -55 o c -50mv output voltage voh vdd = 5v, no load 1, 2 +25 o c, +125 o c, -55 o c 4.95 - v output voltage voh vdd = 10v, no load 1, 2 +25 o c, +125 o c, -55 o c 9.95 - v output current (sink) iol5 vdd = 5v, vout = 0.4v 1, 2 +125 o c0.36-ma -55 o c0.64-ma output current (sink) iol10 vdd = 10v, vout = 0.5v 1, 2 +125 o c0.9-ma -55 o c1.6-ma output current (sink) iol15 vdd = 15v, vout = 1.5v 1, 2 +125 o c2.4-ma -55 o c4.2-ma output current (source) ioh5a vdd = 5v, vout = 4.6v 1, 2 +125 o c--0.36ma -55 o c--0.64ma output current (source) ioh5b vdd = 5v, vout = 2.5v 1, 2 +125 o c--1.15ma -55 o c--2.0ma output current (source) ioh10 vdd = 10v, vout = 9.5v 1, 2 +125 o c--0.9ma -55 o c--1.6ma output current (source) ioh15 vdd =15v, vout = 13.5v 1, 2 +125 o c--2.4ma -55 o c--4.2ma input voltage low vil1 vdd = 10v, voh > 9v, vol < 1v 1, 2 +25 o c, +125 o c, -55 o c -3v input voltage high vih vdd = 10v, voh > 9v, vol < 1v 1, 2 +25 o c, +125 o c, -55 o c +7 - v
7-643 specifications CD14538BMS propagation delay +tr or -tr to q or q tphl1 tplh1 vdd = 10v 1, 2, 3 +25 o c-300ns vdd = 15v 1, 2, 3 +25 o c-220ns propagation delay reset to q or q tphl2 tplh2 vdd = 10v 1, 2, 3 +25 o c-250ns vdd = 15v 1, 2, 3 +25 o c-190ns transition time tthl ttlh vdd = 10v 1, 2, 3 +25 o c-100ns vdd = 15v 1, 2, 3 +25 o c - 80 ns output pulse width q or q c x =.002 f, r x = 100k tw vdd = 5v 1, 2, 3 +25 o c-230 s vdd = 10v 1, 2, 3 +25 o c-232 s vdd = 15v 1, 2, 3 +25 o c-234 s output pulse width c x = 0.1 f r x = 100k tw 1, 2, 3 +25 o c-10.5ms vdd = 10v 1, 2, 3 +25 o c-10.6ms vdd = 15v 1, 2, 3 +25 o c-10.6ms output pulse width c x = 10 f r x = 100k tw vdd = 5v 1, 2, 3 +25 o c - 1.06 s vdd = 10v 1, 2, 3 +25 o c - 1.06 s vdd = 15v 1, 2, 3 +25 o c - 1.07 s minimum retrigger time trr vdd = 5v 1, 2, 3 +25 o c0-ns vdd = 10v 1, 2, 3 +25 o c0-ns vdd = 15v 1, 2, 3 +25 o c0-ns minimum input pulse width +tr, -tr, or reset tw vdd = 5v 1, 2, 3 +25 o c-140ns vdd = 10v 1, 2, 3 +25 o c - 80 ns vdd = 15v 1, 2, 3 +25 o c - 60 ns input capacitance cin any input 1, 2 +25 o c-7.5pf notes: 1. all voltages referenced to device gnd. 2. the parameters listed on table 3 are controlled via design or process and are not directly tested. these parameters are chara cterized on initial design release and upon design changes which would affect these characteristics. 3. cl = 50pf, rl = 200k, input tr, tf < 20ns. table 4. post irradiation electrical performance characteristics parameter symbol conditions notes temperature limits units min max supply current idd vdd = 20v, vin = vdd or gnd 1, 4 +25 o c-25 a n threshold voltage vnth vdd = 10v, iss = -10 a1, 4+25 o c -2.8 -0.2 v n threshold voltage delta ? vnth vdd = 10v, iss = -10 a1, 4+25 o c- 1v p threshold voltage vpth vss = 0v, idd = 10 a1, 4+25 o c0.22.8v p threshold voltage delta ? vpth vss = 0v, idd = 10 a1, 4+25 o c- 1v functional f vdd = 18v, vin = vdd or gnd 1 +25 o cvoh > vdd/2 vol < vdd/2 v vdd = 3v, vin = vdd or gnd propagation delay time tphl tplh vdd = 5v 1, 2, 3, 4 +25 o c - 1.35 x +25 o c limit ns notes: 1. all voltages referenced to device gnd. 2. cl = 50pf, rl = 200k, input tr, tf < 20ns. 3. see table 2 for +25 o c limit. 4. read and record table 3. electrical performance characteristics (continued) parameter symbol conditions notes temperature limits units min max
7-644 specifications CD14538BMS table 5. burn-in and life test delta parameters +25 o c parameter symbol delta limit supply current - msi-2 idd 1.0 a output current (sink) iol5 20% x pre-test reading output current (source) ioh5a 20% x pre-test reading table 6. applicable subgroups conformance group mil-std-883 method group a subgroups read and record initial test (pre burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a interim test 1 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a interim test 2 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a pda (note 1) 100% 5004 1, 7, 9, deltas interim test 3 (post burn-in) 100% 5004 1, 7, 9 idd, iol5, ioh5a, rondel10 pda (note 1) 100% 5004 1, 7, 9, deltas final test 100% 5004 2, 3, 8a, 8b, 10, 11 group a sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group b subgroup b-5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, deltas subgroups 1, 2, 3, 9, 10, 11 subgroup b-6 sample 5005 1, 7, 9 group d sample 5005 1, 2, 3, 8a, 8b, 9 subgroups 1, 2 3 note: 1. 5% parameteric, 3% functional; cumulative for static 1 and 2. table 7. total dose irradiation conformance groups mil-std-883 method test read and record pre-irrad post-irrad pre-irrad post-irrad group e subgroup 2 5005 1, 7, 9 table 4 1, 9 table 4 table 8. burn-in and irradiation test connections function open ground vdd 9v -0.5v oscillator 50khz 25khz static burn-in 1 (note 1) 6, 7, 9, 10 1, 3 - 5, 8, 11 - 13, 15 2, 14, 16 static burn-in 2 (note 1) 6, 7, 9, 10 1, 8, 15 2 - 5, 11 - 13, 14, 16 dynamic burn- in (note 1) - 1, 4, 8, 12, 15 2, 14, 16 6, 7, 9, 10 5, 11 3, 13 irradiation (note 2) 2, 6, 7, 9, 10, 14 1, 8, 15 3 - 5, 11 - 13, 16 note: 1. each pin except vdd and gnd will have a series resistor of 10k 5%, vdd = 18v 0.5v 2. each pin except vdd and gnd will have a series resistor of 47k 5%; group e, subgroup 2, sample size is 4 dice/wafer, 0 failures, vdd = 10v 0.5v
645 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certification. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by int ersil is believed to be accurate and reli- able. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents o r other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its sub sidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com specifications CD14538BMS table 9. functional terminal connections function vdd to term # vss to term # input pulse to term # other connections mono1 mono2 mono1 mono2 mono1 mono2 mono1 mono2 leading-edge trigger/ retriggerable 3, 5 11, 13 4 12 leading-edge trigger/ non-retriggerable 3 13 4 12 5 - 7 11 - 9 trailing-edge trigger/ retriggerable 313 4 12 5 11 trailing-edge trigger/ non-retriggerable 3 13 5 11 4 - 6 12 - 10 note: 1. a triggerable one-shot multivibrator has an output pulse width which is extended one full time period (t) after application of the last trigger pulse. 2. a non-triggerable one-shot multivibrator has a time period (t) referenced from the application of the first trigger pulse. t t input pulse train retriggerable mode pulse width (+tr mode) non-retriggerable mode pulse width (+tr mode) p ower-down mode d uring a rapid power-down condition, as would occur with a p ower-supply short circuit or with a poorly filtered power sup- p ly, the energy stored in c x could discharge into pin 2 or 14. t o avoid possible device damage in this mode, when c x is 0 .5 microfarad, a protection diode with a 1-ampere or higher r ating (1n5395 or equivalent) and a separate ground return f or c x should be provided as shown in figure 1. a n alternate protection method is shown in figure 2, where a 5 1-ohm current-limiting resistor is inserted in series with c x . n ote that a small pulse width decrease will occur however, a nd r x must be appropriately increases to obtain the origi- n ally desired pulse width. figure 1. rapid power-down protection circuit figure 2. alternate rapid power-down protectio n circuit v d d v ss 16 8 r x 2(14) 1(15) v ss c x 0.5 fd + in5395 or equivalent v d d v ss 16 8 r x 2(14) 1(15) c x 0.5 fd + 51 ohms
7-646 CD14538BMS logic diagram figure 3. 1/2 of device shown + - + - = d cl cl ff r1 r2 q q p n p n p n vdd r1 r2 vdd vss comp i comp ii 7 (9) q 6 (10) vdd vss q r2 r1 q cl cl cl cl cl cl r1 r2 vcc cl vdd 16 vss vdd r4 r3 high z vss vdd vss vss vdd 8 vss vdd rx cx vdd vdd 2(14) 1(15) * tr 5(11) 4(12) 3(13) * tr * r *all inputs are protected by cmos protection network ff detail q typical performance characteristics figure 4. typical output low (sink) current characteristics figure 5. minimum output low (sink) current characteristics 10v 5v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 15v 051015 15 10 5 20 25 30 drain-to-source voltage (vds) (v) output low (sink) current (iol) (ma) 10v 5v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = 15v 0 5 10 15 7.5 5.0 2.5 10.0 12.5 15.0 drain-to-source voltage (vds) (v) output low (sink) current (iol) (ma)
7-647 CD14538BMS figure 6. typical output high (source) current characteristics figure 7. minimum output high (source) current characteristics figure 8. typical propagation delay time as a function of load capacitance (+tr or -tr to q or q ) figure 9. typical propagation delay time as a func- tion of load capacitance (reset to q or q ) figure 10. typical transition time as a function of load capacitance figure 11. typical pulse-width variation as a function of supply voltage typical performance characteristics (continued) -10v -15v ambient temperature (t a ) = +25 o c gate-to-source voltage (vgs) = -5v 0 -5 -10 -15 drain-to-source voltage (vds) (v) -20 -25 -30 0 -5 -10 -15 output high (source) current (ioh) (ma) -10v -15v ambient temperature (t a ) = +25 o c 0 -5 -10 -15 drain-to-source voltage (vds) (v) 0 -5 -10 -15 output high (source) current (ioh) (ma) gate-to-source voltage (vgs) = -5v ambient temperature (t a ) = +25 o c supply voltage (vdd) = 5v 10v 15v 020406080100 load capacitance (cl) pf 100 200 300 400 +tr, -tr propagation delay time (tphl, tplh) -ns ambient temperature (t a ) = +25 o c supply voltage (vdd) = 5v 10v 15v 020406080100 load capacitance (cl) pf 100 200 300 400 resetpropagation delay time (tphl, tplh) -n s ambient temperature (t a ) = +25 o c load capacitance (cl) (pf) 0 40 6080100 20 0 50 100 150 200 supply voltage (vdd) = 5v 10v 15v transition time (tthl, ttlh) (ns) ambient temperature (t a ) = +25 o c pulse width variation - percent normalized to vdd = 10v -3 -2 -1 0 1 2 3 4 6 8 10 12 14 16 18 20 vdd supply voltage (volts)
7-648 CD14538BMS chip dimension and pad layout figure 12. typical pulse-width variation as a function of temperature (rx = 100 k ? , cx = 0.1 f) figure 13. typical pulse-width variation as a function of temperature (rx = 100 k ? , cx = 2000pf) figure 14. typical total supply current as a func- tion of output duty cycle figure 15. typical total supply current as a func- tion of load capacitance typical performance characteristics (continued) supply voltage (vdd) = 15v 10v 5v -3 -2 -1 0 1 2 3 -60 -40 -20 0 20 40 60 80 100 120 14 0 ambient temperature ( o c) typical pulse width variation - percent normalized to vdd = 10v, ta = 25 o c supply voltage (vdd) = 5v 10v 5v -60 -40 -20 0 20 40 60 80 100 120 140 ambient temperature ( o c) typical pulse width variation - percent normalized to vdd = 10v, ta = 25 o c -3 -2 -1 0 1 2 3 cl = 50pf, rl = 200k ? rx = 100k ? ambient temperature (t a ) =25 o c one monostable operating supply voltage (vdd) = 5v 15v 18v 10v 1000 100 10 1 0.1 0.01 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 2 6 4 2 8 6 4 2 8 6 4 2 8 6 4 28 6 4 28 6 4 28 6 4 2 0.0001 0.001 0.01 0.1 1 10 100 output duty cycle (%) total supply current ( a) 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 2 8 6 4 28 6 4 28 6 4 28 6 4 28 6 4 2 1000 100 10 0 idd current ( a) 50% dc cx capacitance (pfs) 10 100 1000 10k 100k rx = 100k ? ta = +25oc supply voltage (vdd) = 15v 5v 10v dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. grid graduations are in mils (10 -3 inch) metallization: thickness: 11k ? ? 14k ?, al. passivatio n: 10.4k? - 15.6k ? , silane bond pads: 0.004 inches x 0.004 inches min die thickness: 0.0198 inches - 0.0218 inches
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